1. Field of the Invention
The invention relates generally to gain control amplifier circuits and, more particularly, to a feedback technique which improves the linearity when switching from a high gain mode to one or more lower gain modes.
2. Description of the Prior Art
Variable gain amplifiers ("VGA's") are used in numerous electronic products such as global positioning (GPS) receivers, wireless local area networks and mobile communication devices, such as cordless and cellular phones. In particular, VGA's are used in the various parts of such devices, for example, in the radio frequency (RF) input stage, intermediate frequency (IF) and low frequency or baseband circuits of these devices.
The linearity of a circuit may be defined by various parameters. For example, the input third-order intercept point represents third-order non-linearity in the transfer function of a circuit. Due to the third-order non-linearity, two undesired signals in adjacent channels generate output third-order intermodulation products (IM3) which can corrupt the desired signal at the output. The power of the desired signal at the output of a linear circuit increases linearly with the input power of the circuit. However, the power of the output IM3 increases with the cube of the input power. The input third-order intercept point is the input power level, at which the power of the desired signal at the output of a circuit is equal to the power of the output IM3.
FIG. 1 shows a typical low-noise amplifier (LNA) 10 for amplifying input signals, such as radio-frequency signals propagating through receiving circuitry of a wireless system, such as a cellular telephone. A signal input RF.sub.in is provided for receiving an input signal from a source, such as a tuner or the previous amplifier stage. The input signal is supplied to the base of an NPN junction transistor Q1. A degeneration impedance Ze is coupled between the emitter of the transistor Q1 and a ground terminal. The transistor Q1 and the impedance Ze function as a common-emitter transconductance stage.
An NPN junction transistor Q2 is connected to the transistor Q1 in a cascode configuration. The emitter of the transistor Q2 is connected to the collector of the transistor Q1. The base of the transistor Q2 is supplied with bias voltage from a bias circuit which can be either on chip or off chip. A resistor R1 and an inductor L1 are coupled between the collector of the transistor Q2 and a source of collector voltage Vcc. A capacitor C1 is arranged between the collector of the transistor Q2 and an output RF.sub.out of the low noise amplifier 10.
The resistor R1 is an output-matching resistor that functions to match the output impedance of the low noise amplifier 10 with the impedance of a load coupled to the output RF.sub.out. The inductor L1 and capacitor C1 form an impedance transformation network that transforms the output impedance defined by the resistor R1 to match the impedance of the load. The inductor L1 also serves as a pull-up inductor that increases the allowable voltage at the collector of the transistor Q2.
The gain of the amplifier of FIG. 1 is controlled in discrete steps by using a well-known current dividing or splitting technique. A switch in the form of an NPN transistor Q3 having its emitter coupled to the collector of the transconductance device Q1 and its collector coupled to the power supply Vcc is provided with a control signal at its base B to render the switch conductive or non-conductive. When the switch Q3 is in the non-conductive state, the amplifier is in the high gain mode and all of the current from the transconductance stage is delivered to the output RF.sub.out. When the switch Q3 is conductive, the amplifier is in a reduced gain mode, as current is diverted from the output and dumped to the power supply by the switch Q3, thereby reducing the gain at the output RF.sub.out relative to the input RF.sub.in. In other words, current from the transistor Q2 is split into two paths, with some of the current diverted through the transistor Q3 and the remaining current provided to the output. In this current splitting technique, the gain step between the two gain modes depends on the device size ratios between the transistors Q2 and Q3 (with all emitters connected to the same node). This gain control scheme can be expanded by connecting additional transistors in parallel with transistors Q2 and Q3 (with all emitters connected to the same node).
A disadvantage of the gain control scheme of FIG. 1 is that the VGA has the same linearity in both high and lower gain modes. In many applications, the VGA is required to have higher linearity when the VGA is switched from the high to the lower gain modes. When the VGA is switched to lower gain modes, it is typically because of higher input signal power, so increased linearity is desired.
It would be desirable to create a new technique that improves the linearity of a VGA when it is switched from a high gain mode to a lower gain mode.